The invention generally relates to parallel processing computers, and, more particularly, to such computers containing a multiple instruction stream processing architecture.
Parallel processing computers are generally designed to implement one of two architectures: (1) Single Instruction Multiple Data stream (SIMD) architecture, and (2) Multiple Instruction Multiple Data stream (MIMD) architecture. A computer having a SIMD architecture is generally referred to as a SIMD computer and a computer having a MIMD architecture is generally referred to as a MIMD computer.
Typically, a parallel processing computer having either architecture contains a plurality of processors coupled to one another by two buses. Specifically, a data bus, carrying a data stream to each processor, and an instruction bus, carrying an instruction stream to each processor. The processors typically share local memory via the data bus such that the processors may share data.
Specifically, in a SIMD computer, a single source program is compiled and executed by all the processors comprising the computer. As such, all the processors simultaneously execute an identical instruction. However, the data supplied via the data bus to each processor differs from processor to processor. The processors in such a system are tightly coupled to maintain synchronous operation of the various processors while each processor independently operates upon its data stream.
In contrast, a MIMD computer has either a single compiled source program executing asynchronously upon each of the processors or has separately compiled source programs executing upon individual processors. Typically, the processors are decoupled and execute instructions independent of the other processors within the computer. As such, to facilitate such independent program execution, most MIMD computers have an instruction memory and program sequencer logic associated with each processor. Also included with each processor, typically on the same chip with the processor, are instruction and data caches. These caches are used to alleviate possible memory bandwidth contention that can arise when multiple processors asynchronously access a shared local memory.
Typically, MIMD computers execute different instructions (or routines of instructions) on different processors using different data streams. After each processor has completed its task (routine or instruction), the processors wait until all the other processors have completed their tasks. Thereafter, the processors are each synchronized to one another and are capable of passing data amongst themselves. Once the exchanged data is available to the processors, i.e., stored in the shared local memory, the processors again independently process this data. This process of repeated independent processing, synchronization, data exchange, independent processing and so on is repeated until the processors have exhausted their instructions.
Recently, to provide both synchronous and asynchronous program execution, computers having combined SIMD/MIMD architectures have been developed. Such combined architecture computers typically operate as SIMD computers for most functions. However, individual processors can be selectively decoupled from the other processors to perform individual tasks, i.e., execute a separate compiled source routine, and provide the result to the other processors. However, to maintain processor synchronization while the MIMD task is being processed, the other processors (those not performing the MIMD task) wait until the MIMD task is complete and, thereafter, all the processors synchronously continue processing. Consequently, processing efficiency in the combined architecture computer is reduced as compared to a solely SIMD or MIMD computer.
Disadvantageously, present mixed architecture computers lack apparatus for easily synchronizing (resynchronizing) the processors to facilitate processing of independent and simultaneous SIMD and MIMD instructions. As such, they are task oriented and must have some processors wait until the MIMD task is complete before continuing with SIMD operations.
Therefore, a need exists in the art for a parallel processing computer capable of asynchronously and simultaneously executing MIMD and SIMD instructions. Such a computer must be capable of receiving and storing MIMD instructions and have a selectable processing mode (SIMD or MIMD mode selection) associated with each processor within the computer.